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DS1808 Dual Log Digital Potentiometer
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FEATURES
Two 32-position log-tapers 60dB attenuation range: -1dB per step (12 taps) -2dB per step (12 taps) -3dB per step (8 taps) -90dB low-end attenuation 2-Wire Interface Control Power Supply: Dual 12V Maximum Voltage Across Potentiometers: 12V Standard Resistance Value: 45kW Packages: 16-Pin SOIC Operating Temperature: -40oC to +85oC
PIN ASSIGNMENT
GND A2 A1 VB A0 W0 L0 H0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VCC SCL SDA CE W H1 L1

16-Pin SOIC (150-mil)
ORDERING INFORMATION
DS1808Z-050 +85C 45k 16-Pin SOIC -40C to
PIN DESCRIPTION
VCC VB VDD H0, H1 L0, L1 W0, W1 SDA SCL /CE GND A0, A1, A2 - +12V Supply - -12V Supply (substrate bias) - 5V Digital Supply - High-end Terminals - Low-end Terminals - Wiper Terminals - 2-Wire Serial Data Input/Output - 2-Wire Clock Input - 2-Wire Interface Enable - Ground - Address Pins
DS1808Z-050/T&R 16-Pin SOIC -40C to +85C 45k
DESCRIPTION
The DS1808 is a dual-channel, digitally controlled, log-taper potentiometer. Each potentiometer is comprised of 32 wiper terminal positions plus a mute position. The device has three accessible potentiometer terminals that include the high-side terminal (H), the low-side terminal (L), and the wiper terminal (W). The resolution of the DS1808 is shown in Figure 8 and represents 1dB per step for the first 12 taps, 2dB per step for the next 12 taps and 3dB per step for the bottom 8 taps, providing a total attenuation range of 60dB. The mute position of the DS1808 provides greater than 90dB of attenuation. The wiper position on the resistor ladder is selected via a 6-bit register, whose value is controlled by the industry-standard 2-wire interface. The interface consists of two control signals: SDA and SCL. The DS1808 is available in a standard 45kW resistor value. The DS1808 is specified to operate over the industrial temperature range (-40oC to +85oC) and is available in the 16-pin SOIC package. The DS1808 was designed for low-cost, stereo volume control applications. The device is specified to operate from 12V 10% supplies and accept a maximum input signal range of 12V.
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DS1808
DS1808 BLOCK DIAGRAM Figure 1
W0 H0 0dB 0dB W1 H1
60dB L0 SDA SCL Control Logic >90dB
60dB >90dB L1 Address Lines A0 - A2 CE
VCC (+12V Supply) GND Power Supply VB (-12V Supply) VDD (5V Supply)
PIN DESCRIPTIONS
VCC - Power Supply Terminal. This pin acts as the positive rail. The DS1808 will support positive supply voltages ranging from 5 to 13.2 volts. When VCC-VB is less than 8 volts the series wiper resistance will increase up to 1kW. The value of VDD should never exceed VCC. VB - Substrate Bias Supply. This pin acts as a negative rail. The DS1808 will support negative voltages ranging from 0 to -13.2 volts. When VCC-VB is less than 8 volts the series wiper resistance will increase up to 1kW. VDD - DC Supply Terminal. 5V DC voltage supply. The value of VDD should never exceed VCC. GND - Ground Terminal. SDA - 2-wire serial data interface. The serial data pin is for serial data transfer to and from the DS1808. The pin is open drain and may be wire-ORed with other open drain or open collector interfaces. SCL - 2-wire serial clock interface. The serial clock input is used to clock data into the DS1808 on rising edges and clock data out on falling edges. /CE - Port Enable Pin. When active (/CE=0), the port inputs SDA and SCL are recognized by the device. If inactive (/CE=1), the port input pins SDA and SCL are disabled making 2-wire communication impossible.
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A0, A1, A2 - Address Inputs. These input pins specify the address of the device when used in a multidropped configuration. Up to eight individual DS1808s may be addressed on a single 2-wire bus. H0, H1 - These are the high-end terminals of the potentiometers. For both potentiometers, it is not required that these terminals be connected to a potential greater than the low-end terminal of the potentiometer. Voltage applied to the high end of the potentiometers cannot exceed the power supply voltage, VCC, or go below VB. L0, L1 - These are the low-end terminals of the potentiometers. It is not required that these terminals be connected to a potential less than the high-end terminals of the pot. Voltage applied to the low end of the potentiometers cannot exceed the power-supply voltage, VCC, or go below VB. W0, W1 - Wiper of the Potentiometer. This pin is the wiper terminal of the potentiometer. Voltage applied to either wiper terminal cannot exceed the power-supply voltage, VCC, or go below VB.
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DS1808
OPERATION
The DS1808 is a dual-channel, digitally controlled, logarithmic potentiometer. Each potentiometer has three accessible terminals, which include H, L, and W. Between each resistor element is a tap-point that is multiplexed to the wiper terminal, W. A block diagram of the DS1808 is shown in Figure 1. Potentiometer Characteristics The DS1808 is a volatile device and always powers-up with the wiper positions set to the mute position (33-decimal) with 90-dB of signal attenuation. The resistor section of the DS1808 is composed of two 32position resistor arrays that provide a logarithmic attenuation. The resistor section of the DS1808 provides a typical 50kW end-to-end resistance between the H terminal and the L terminal. The wiper terminal will have a total possible 34 tap positions. The 34th position is considered the mute position and will provide attenuation in excess of 90dB. The potentiometers of the DS1808 are closely matched and provide excellent tracking. Interchannel matching for the device is specified to provide less than 0.5dB. Tap-to-tap tolerances for the device are specified to provide less than 0.5dB. Power Supplies The DS1808 is designed to be powered from dual 12V supplies. The maximum input signal that can be placed across the potentiometer sections is 12V. The device can also be powered using a single +12V power source. When using the device in a single supply configuration, VB is set to 0V and the maximum potentiometer input signals are restricted to single supply voltage rails. Controlling the Potentiometers All writing and reading to the potentiometers is done with the industry standard 2-wire interface, which includes pins SDA and SCL.
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bi-directional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the start and stop conditions. The DS1808 operates as a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following I/O terminals control the 2-wire serial port: /CE, SDA, SCL, A0, A1, A2. Timing diagrams for the 2-wire serial port can be found in Figures 2 and 7.
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DS1808
2-WIRE SERIAL PROTOCOL
The following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low while the clock is high defines a start condition. Stop data transfer: A change in the state of the data line from low to high while the clock line is high defines the stop condition. Data valid: The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9th bit. Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1808 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an "acknowledge" after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the stop condition. 1. The following occurs when data is transferred from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2. The following occurs when data is transferred from a slave transmitter to a master receiver. The master transmits the first byte (the command/control byte) to the slave. The slave then returns an acknowledge bit. Next, follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" can be returned.
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The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended with a stop condition or with a repeated start condition. Since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. The DS1808 may operate in the following two modes: 1. Slave receiver mode: Serial data and clock are received through SDA and SCL respectively. After each byte is received, an acknowledge bit is transmitted. Start and stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave (device) address and direction bit. 2. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1808 while the serial clock is input on SCL. Start and stop conditions are recognized as the beginning and end of a serial transfer. 3. Slave Address: command/control byte is the first byte received following the start condition from the master device. The command/control byte consists of a 4-bit control code. For the DS1808, this is set as 0101 binary for read/write operations. The next three bits of the command/control byte are the device select bits or slave address (A2, A1, A0). They are used by the master device to select which of eight devices is to be accessed. When reading or writing the DS1808, the device select bits must match the device select pins (A2, A1, A0). The last bit of the command/control byte (R/W) defines the operation to be performed. When set to a 1, a read operation is selected, and when set to a 0, a write operation is selected. Following the START condition, the DS1808 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the 0101 control code, the appropriate device address bits, and the read/write bit, the slave device outputs an acknowledge signal on the SDA line.
COMMAND AND PROTOCOL
The command and protocol structure of the DS1808 allows the user to read from or write to the potentiometer(s). Additionally, the 2-wire command/protocol structure of the DS1808 will support eight different devices and a maximum of 16 channels that can be uniquely controlled. The command structures for the device are presented in Figures 3, 4, 5, and 6. Potentiometer data values and command/control values are always transmitted most significant bit (MSB) first. During communications, the receiving unit always generates the acknowledgement.
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READING THE DS1808
As shown in Figure 4, the DS1808 provides one read command operation. This operation allows the user to read both potentiometers. To initiate a read operation, the R/W bit of the command/control byte is set to 1. Communication to read the DS1808 begins with a start condition, which is issued by the master device. The command/control byte from the master device will follow the start condition. Once the command/control byte has been received by the DS1808, the part will respond with an acknowledge. When the master has received the acknowledge from the DS1808, the master can then begin to receive wiper data. The value of the wiper of potentiometer-0 will be the first returned from the DS1808. It will then be followed by the value of potentiometer-1. Once the 8-bits of potentiometer-0 have been transmitted, the master will need to issue an acknowledge, unless it is the only byte to be read, in which case the master issues a `not acknowledge.' If desired, the master may stop the communication transfer at this point by issuing the stop condition. However, if the value of the remaining potentiometer is needed, transfer can continue by clocking the 8 bits of the potentiometer-1 value, followed by a not acknowledge.
WRITING TO THE DS1808
A data flow diagram of the DS1808 is shown in Figure 5. The DS1808 has one write command that is used to change the position of the wiper(s). All write operations begin with a START from the master, followed by a command/control byte. The R/W bit should be written to 0b, which initiates a write command. Once the command/control byte has been issued and the master receives the ACKNOWLEDGE from the DS1808, potentiometer wiper data is transmitted to the DS1808 by the master device.
Figure 2
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DS1808
Figure 3
Figure 4
Figure 5
Figure 6
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Figure 7
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TAP/ATTENUATION TABLE Figure 8
TAP POSITION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ATTENUATION (dB) 0 1 2 3 4 5 6 7 8 9 10 11 12 14 16 18 20 22 24 26 28 30 32 34 36 39 42 45 48 51 54 57 60 90
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ABSOLUTE MAXIMUM RATINGS*
Voltage on All Pins (except /CE, SDA, SCL, A0, A1, and A2) Relative to Ground Voltage on Pins /CE, SDA, SCL, A0, A1, and A2 Operating Temperature Storage Temperature Soldering Temperature VB - 0.3V to VCC + 0.3V GND - 0.3V to VDD + 0.3V -40C to +85C -55C to +125C See J-STD-020A specification
*This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Analog Supply Voltage Substrate Bias Voltage Digital Supply Voltage Resistor Inputs SYMBOL VCC VB VDD L,H,W MIN +4.5 -13.2 4.5 VB TYP MAX +13.2 0 5.5 VCC
(-40C to +85C)
UNITS V V V V NOTES 1, 3 3 3
DC ELECTRICAL CHARACTERISTICS (-40C to +85C/VCC, VB=5V to 13.2V/VDD=4.5V to 5.5V)
PARAMETER Supply Current Active Input Leakage Input Logic 1 Input Logic 0 Power Up Time (Port Active) Standby Current (VCC, VB) Active Supply Current (VB) SYMBOL ICC ILI VIH VIL tPU ISTBY 8V 12V -1 0.7VDD GND-0.3 CONDITION MIN TYP MAX 2 +1 VDD + 0.3V 0.8 1 15 25 2.0 UNITS mA
mA
NOTES 12, 13
V V ms
mA
2 2
4 12, 13
mA
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ANALOG RESISTOR CHARACTERISTICS (-40C to +85C/VCC, VB=5V to 13.2V/VDD=4.5V to 5.5V)
PARAMETER End-to-End Resistance Total Resistance Absolute Linearity Relative Linearity Interchannel Matching -3 dB Cutoff frequency Output Noise (20Hz to 20kHz, Grounded Input, Tap = -6dB) Total Harmonic Distortion Interchannel Isolation (20Hz to 20kHz, Grounded Input, Tap = -6dB) Mute Position Wiper Resistance Wiper Current Resistor Inputs Temperature Coefficient RW IW L,H,W VB 750 THD+N fcutoff -0.5 -0.25 -0.5 5 2.2 SYMBOL CONDITION MIN -20 45kW +0.5 +0.25 +0.5 LSB LSB dB MHz mVRMS 9 10 TYP MAX +20 UNITS % NOTES
0.001 -100
%
dB
-90 300 600 1 VCC
dB
W
mA V
ppm/C
11
CAPACITANCE
PARAMETER Input Capacitance SYMBOL CIN CONDITION MIN TYP MAX 10 UNITS pF NOTES
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AC ELECTRICAL CHARACTERISTICS
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Hold Time (repeated) START Condition Low Period of SCL Clock High period of SCL Clock Data Hold Time Data Set-Up Time Start Set-Up Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Set-Up Time for STOP Condition Capacitive Load for Each Bus Line SYMBOL fSCL tBUF tHD:STA tLOW t HIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB CONDITION Fast Mode Standard Mode
(-40oC to +85oC, VDD=4.5V to 5.5V)
MIN 0 0 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0 0 100 250 0.6 4.7 20+0.1 CB 20+0.1 CB 0.6 4.0 TYP MAX 400 100 UNITS kHz ms ms ms ms 0.9 ms ns ms 300 1000 300 300 ns ns ms 400 pF 8 NOTES 5 5 6, 5 5 5 5,7 5 5 8 8
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NOTES:
1. All voltages are referenced to ground. 2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off. 3. The value of VDD should never exceed VCC, including during power-ups. VCC must be applied before either VDD or VB. VDD and VB can then follow in any order. 4. ISTBY specified for VDD equal to 5.0V. Control port logic pins are driven to the appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VDD for the corresponding inactive state. 5. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. 6. After this period, the first clock pulse is generated. 7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 8. CB - Total capacitance of one bus line in picofarads, timing referenced to (0.9)(VDD) and (0.1)(VDD). 9. Absolute linearity is used to measure expected wiper voltage as determined by wiper position. 10. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper positions. 11. When used as a rheostat or variable resistor the resistance temperature coefficient is: 750ppm/C. When used as a voltage divider or potentiometer, the output voltage temperature coefficient approaches 30 ppm/C. 12. ICC specified with SDA pin open. 13. Maximum ICC is dependent on clock rates.
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TYPICAL OPERATING CHARACTERISTICS (VCC = 12V, VB = -12V, VDD = 5V, T = +25C, unless otherwise specified.)
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TYPICAL OPERATING CHARACTERISTICS (cont.) (VCC = 12V, VB = -12V, VDD = 5V, T = +25C, unless otherwise specified.)
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TYPICAL OPERATING CHARACTERISTICS (cont.) (VCC = 12V, VB = -12V, VDD = 5V, T = +25C, unless otherwise specified.)
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